Monolithic integrated voltage stabilizer circuit with tapped diode string

ABSTRACT

This relates to a monolithic integrated voltage stabilizing circuit containing a stabilizing chain of series connected diodes at the connection points of which several stabilized voltages are tapped. All stabilized voltages below the momentary value of the supply voltage are always present. Additional constant current source transistors form a multi-collector lateral pnp transistor.

United States Patent [191 Schilling et al.

[ MONOLITHIC INTEGRATED VOLTAGE STABILIZER CIRCUIT WITH TAPPED DIODESTRING [75] Inventors: Harald Schilling; Wolfgang Hoehn,

both of Freiburg, Germany [73] Assignce: ITT Industries Inc., New York,

[22] Filed: July 9, 1973 [21 1 Appl. No.: 377,477

[52] US. Cl 323/8, 307/297, 317/23 SD, 323/22 Z, 323/25 [51] Int. Cl.G05f 3/14 [58] Field of Search 307/297, 318; 323/1, 8, 323/22 T, 22 Z,23, 25; 317/23 SD [56] References Cited UNITED STATES PATENTS 3,237,0782/1966 Mallory 323/22 T June 25, 1974 3,648,153 3/1972 Grzlf 307/297 X3,742,338 6/1973 Sugano ct a1 323/22 T OTHER PUBLICATIONSElectronies-Multi-Emittcr lCs Stabilize Voltages in Solid State Turnersby Eckstein et al., pp. 91-93 Dec. 8, 1969.

Primary ExaminerGerald Goldberg Attorney, Agent, or Firm.lohn T.OHalloran; Menotti J. Lombardi, Jr.; Vincent lngrassia [5 7] ABSTRACTThis relates to a monolithic integrated voltage stabilizing circuitcontaining a stabilizing chain of series connected diodes at theconnection points of which sev eral stabilized voltages are tapped. Allstabilized voltages below the momentary value of the supply voltage arealways present. Additional constant current source transistors form amulti-collector lateral pnp transistor.

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MONOLITHIC INTEGRATED VOLTAGE STABILIZER CIRCUIT WITH TAPPED DIODESTRING BACKGROUND OF THE INVENTION This invention relates to amonolithic integrated voltage stabilizing circuit from which severalstabilized voltages can be tapped, and more particularly to a voltagestabilizing circuit wherein all stabilized voltages below the momentaryvalue of the supply voltage are always present.

The present invention starts from a monolithic integrated voltagestabilizing circuit which is contained as a subcircuit in thecommercially available series regulating circuit CA 3085. The internalcircuit of this component is shown, for example, in the LinearIntegrated Circuit D.A.T.A.-Book, 7th Edition, Spring 1972, N.J., 1971,of Derivation and Tabulation Associates Inc., on p. 121 in FIG. F 088.In this circuit diagram, the circuit portion serving as the startingpoint for the invention is shown on the left.

Known stabilizing circuits have the disadvantage that the stabilizationof the voltages which can be tapped does not set in until the supplyvoltage is slightly higher than the highest voltage to be stabilized. Itis frequently necessary that the lowest voltage to be stabilized set inas early as possible after the supply voltage is turned on, toimmediately render basic functions of the integrated circuitoperational. The voltage stabilizing circuit of the above kind hasanother disadvantage in that short-time drops in supply voltage such asfrequently occur, for example, in onboard supplies of vehicles andaircraft may put the stabilizing function of the series connection outof operation, whereby all voltages to be stabilized fail.

SUMMARY OF THE INVENTION It is therefore the object of the presentinvention to provide a voltage stabilizing circuit of the above referredto kind wherein the voltages to be stabilized by means of the seriesconnection remain stabilized as long as the respective supply voltagelies' above the value to be stabilized. In other words, the inventionhas for its object to provide a voltage stabilizing circuit in which allthose voltages to be stabilized are still present which, when the supplyvoltage drops, lie below the reduced value.

According to a broad aspect of the invention, there is provided amonolithic integrated voltage stabilizing circuit comprising: a sourceof supply voltage; a plurality of series connected reference elementshaving tapping points from which stabilized voltages can be tapped; afirst resistor; a first npn transistor having a base connected to thetapping point of the lowest voltage to be stabilized and having anemitter coupled via said first resistor to ground; a first pnp diodeconnected transistor having an emitter coupled to said source of supplyvoltage and having a base and collector coupled together and to thecollector of said first npn transistor; a starting resistor coupledbetween the tapping of the lowest voltage to be stabilized and saidsource of supply voltage; a second pnp transistor having an emittercoupled to said source of supply voltage, a base coupled to the base ofsaid first pnp transistor and a collector coupled to the base of saidnpn transistor via said plurality of series connected referenceelements; and a plurality of additional pnp transistors (T T each havingemitters coupled to said source of supply voltage, each having basescoupled together and to the base of said second pnp transistor and eachof said plurality having a collector coupled to one of said tappingpoints of said series connected reference elements.

Using this arrangement each voltage to be stabilized is maintained aslong as the supply voltage does not drop below the value to bestabilized. This has the advantage that, in the integrated circuitfitted with the circuit according to the invention, existing memoryfunctions, for example, remain undisturbed as long as the supply voltagedoes not drop below the lowest voltage to be stabilized.

The voltage stabilizing circuit acording to the invention can beadvantageously realized by designing all pnp transistors as a singlemulticollector lateral transistor. This lateral transistor isadvantageously designed so that the emitter region is strip-shaped andlocated in the center of the base region, that the individual collectorregions are located along the circumference of, and opposite to, theemitter region, and that the collector region connected to the tap ofthe lowest voltage to be stabilized additionally encloses the othercollector regions in the form of a closed frame.

However, as will be explained in detail below, the single lateraltransistor also may advantageously be designed so that the emitterregion is strip-shaped and located in the center of the base region,that the collector regions of the first pnp transistor, of the secondpnp transistor, and of the pnp transistor associated with the tap of thelowest voltage to be stabilized are arranged along the circumference of,and opposite to, the emitter region, that the collector region connectedto the second-highest voltage to be stabilized lies opposite to thecollector region of the second pnp transistor without lying opposite tothe emitter region, that the collector region connected to thethird-highest voltage to be stabilized lies opposite to the collectorregion connected to the second-highest voltage to be stabilized withoutlying opposite to the emitter region, etc., up to the collector regionconnected to the second-lowest voltage to be stabilized, and that thecollector region connected to the lowest voltage to be stabilizedadditionally encloses the other collector regions in the form of aclosed frame.

Both of the above preferred embodiments of the lateral transistor areparticularly well suited for the purpose stated if the collector regionsedge portions lying opposite to the emitter region are equally long.

The above objects and features will be better understood from thefollowing detailed description taken in conjunction with theaccompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the essential parts of avoltage stabilizing circuit according to the prior art;

FIG. 2 shows the voltage stabilizing circuit according to the inventionin its general form;

FIG. 3 shows the voltage stabilizing circuit according to the inventionfor two voltages to be stabilized;

FIG. 4 shows one preferred embodiment of the arrangement of theindividual regions of the pnp transistors;

FIG. 5 shows another preferred embodiment of the arrangement of theregions of the pnp transistors; and

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, the knownstabilizing circuit consists of the reference element Z, whose voltage Urepresents the voltage to be stabilized. The current flowing through thereference element is essentially determined by the resistance value ofthe resistor R1, which is connected as the emitter resistor of the npntransistor T. Via the diode-connected pnp transistor T whosecollector-emitter path connects the collector of the npn transistor T tothe positive terminal of the supply-voltage source U and via the pnptransistor T whose baseemitter path is connected in parallel to thebase-emitter path of the pnp transistor T it is ensured that a currentequal to the collector current of the npn transistor T also flows viathe collector of the pnp transistor T and thus through the referenceelement Z. The resistor R2, which connects the reference element to thepositive terminal of the supply-voltage source, serves as a startingresistor to ensure, when the supplyvoltage source is turned on, that thestabilizing circuit assumes the stable state. As can be seen, thestabilizing circuit exhibits a bistable behavior, with an unstable statebeing the second of the bistable states. Instead of the startingresistor, it is also possible to provide for pulsed tum-on.

As can be seen, the known circuit principle shown in FIG. 1 makes use ofthe principle of a constant current source as shown in IEEE Journal ofSolid-State Circuits," June 1969, p. 114, FIG. 8, through the two pnptransistors.

For the voltage supply of monolithic integrated circuit arrangements,the known circuit principle can be extended by using not only one singlereference element but a series connection of several reference elements,whereby different stabilized voltages can be tapped from the respectivejunction points of the individual reference elements. Used as referenceelements are, in known manner, diode-connected transistors operatedeither in the forward direction or in the reverse direction up to thebreakdown region.

FIG. 2 shows the voltage stabilizing circuit according to the inventionin its general form. The interconnection of the two pnp transistors Tand T of the starting resistor R2, of the npn transistor T, and of theemitter resistor R1 is identical to that of FIG. 1, while the referenceelement 2 of FIG. 1 has been replaced by the series connection of thereference elements Z Z Z,, Z,, and Z The order of numbering of thecomponents is chosen so that the reference element Z is connected to thecollector of the second pnp transistor T while the last referenceelement Z, of the series connection is connected to ground.

From the series connection of these reference elements, as manystabilized voltages can be tapped as there are reference elements. InFIG. 2, these voltages are designated U U U,,,.,, the respective voltageas viewed from the collector of the second pnp transistor T being tappedahead of the reference element of the same index.

According to the invention, for solving the problem underlying theinvention and stated above, each tapping point of the series connectionof the reference elements, i.e., each junction point of two adjacentreference elements, is connected via an additional pnp tran sistor tothe positive terminal of the supply-voltage source U with the collectorof this respective transistor connected to the respective tapping point,teh emitter connected to the supply-voltage source U and the baseconnected to the bases of the first and second pnp transistors T and T,,respectively. Thus, the baseemitter path of the respective additionalpnp transistor is connected in parallel to the base-emitter paths of thefirst and second pnp transistors.

In detail, the junction point of the reference elements Z and Z has thecollector of the additional pnp transistor T connected thereto, or, inother words, the collector of the additional pnp transistor, as viewedfrom the collector of the second pnp transistor T is connected ahead ofthe respective reference element of the same index.

Thus, the collector of the additional pnp transistor T,, is connectedahead of the reference elements Z,, i.e., to the junction point of thisreference element with the reference element Z,, (not shown in FIG. 2).Accordingly, the last two additional pnp transistors T,, and T areconnected to the junction points between the reference elements Z,, Z,,and Z,, Z respectively.

For the graphic representation of the reference elements Z 2,, in FIG.2, the symbols for zener diodes and diodes were chosen to indicate thatboth types of components may be used to form the series connection ofthe reference elements. In this case, the diodes are forward-biased, andthe zener diodes reversebiased. The reference elements Z Z are shown asforwardbiased diodes, while the reference elements Z,, Z, and Z,, areshown as zener diodes. However, this order is arbitrary, and any otherorder may be chosen, in which case, however, the last reference element2,, should be a zener diode and not a forward-biased diode in order forthe current in the resistor R1 to be better adjustable.

FIG. 3 shows the circuit arrangement derived from the general form ofthe inventive stabilizing circuit of FIG. 2 for two voltages U and U tobe stabilized. In this case, the series connection consists of the tworeference elements Z and Z for which the zener-diode symbols werechosen. Thus, the series connection of the reference elements has asingle tapping point, from which the stabilized voltage U is tapped.According to the invention, this point is connected via thecollectoremitter path of the additional pnp transistor T to the positiveterminal of the supply-voltage source U The specific coupling of theother components of FIG. 3 is identical to that of FIG. 2.

While FIGS. 1 to 3 are circuit diagrams of the voltage stabilizingcircuit according to the invention, FIGS. 4 to 6 show plan views ofadvantageous structures of the pnp transistors in the monolithicintegrated circuit. Particularly advantageously, the pnp transistors arerealized as a single lateral transistor with a suitable number ofindividual collectors.

The characteristics, structure, and operation of such lateraltransistors are known from Proceedings of the IEEE, Dec. 1964, pp. 1491to 1495. By a lateral transistor of a monolithic integrated circuit atransistor is understood whose current flowing from the emitter via thebase to the collector flows substantially in parallel to the mainsurface of the integrated circuit, while, in contrast, the transistorscommonly formed in monolithic integrated circuits having acollector-emitter current path vertical to this surface.

Such lateral transistors are particularly suitable for the realizationof pnp transistors in monolithic integrated circuits which usually havenpn transistors with the above-mentioned vertical current flow. Toaccomplish this, individual regions separated from each other by p-typematerial are first fabricated in the commonly n-type, mostly epitaxiallygrown region of the monolithic integrated circuit by so-calledinsulation diffusion.

These regions, separated from each other by pn junctions, can be usedeither for the construction of an npn transistor or for the constructionof a lateral pnp transistor. In this case, the n-type region is activeas the collector of the npn transistor or as the base of the lateraltransistor. By diffusion of impurities producing p-type conductivity,which diffusion forms the base region in the npn transistor, the lateraltransistors p-type regions for the emitter region and for the collectorregion are produced which are located at the semiconductor surface sideby side and at a specified distance. According to the referencementioned above, the location of the collector region may be chosen sothat the collector region surrounds the emitter region as ageometrically closed configuration.

The use of several pnp transistors in an integrated circuit which areinterconnected after the manner of a multiple constant current source isalso known in the art, see IEEE Journal of Solid-State Circuits, Apr.1972, pp. 105 to II 1, especially FIG. 9 on p. I07. This figure shows astrip-shaped emitter region which is surrounded by the individualcollector regions.

Unlike this structure of a lateral transistor with several collectors,the lateral transistor for the realization of the stabilizing circuitaccording to the invention is designed so that, although, as shown inthe different embodiments of FIGS. 4 to 6, individual collectors arearranged along, and opposite to, the likewise stripshaped emitter regionE, one of these collector regions, namly the collector region C, of theadditional pnp transistor T, connected to the lowest voltage U, to bestabilized, lies opposite to the emitter region E and encloses the othercollector regions like a frame with the portion C,,.

The embodiment of the lateral transistor of FIG. 4 shows the insulatingregion I, which encloses the entire structure like a frame and isobtained by the insulation diffusion mentioned above. Located withinthis insulating region is the base region B, whose right edge isprovided with the base contact B. The broken line indicates theextension of the so-called buried layer BL, which is located below theindividual regions in the semiconductor body and, as is well-known,serves to reduce bulk resistances.

In the center of the base region, the strip-shaped emitter region E canbe seen which is hatched toward the right and surrounded by theindividual collector regions, hatched toward the left, so that,according to the current flowing through the individual collectors, amore or less small portion of the collector region lies opposite to theemitter region, because the edge length of that portion of therespective collector region which additional reference elements Z liesopposite to the emitter region determines the value of the currentflowing through the collector.

In the embodiment of FIG. 4, the arrangement of the collector regions CC,, is arbitrary. For example, the collector region C of the first pnptransistor T is shaped like a U enclosing one end of the emitter region,while the collector region C, C,,.{ are also stripshaped and lieopposite to the emitter region.

In the embodiment of FIG. 4, the collector region C,,, which, with theportion C,,, encloses the other collector regions like a frame, has twoportions lying opposite to the emitter region E and thus can take overcurrent from this emitter region. However, this embodiment is notmandatory; it is also possible to provide this collector region withonly one single portion lying opposite to the emitter region B.

As can be seen, the lateral transistor of FIG. 4 contains six individualcollector regions. Thus, the collector region C,, is identical to thecollector region C the collector region C,, to the collector region Cand the collector region C, to the collector region C the referencecharacters being added in brackets.

The stabilizing circuit according to the invention as well as theembodiment of the lateral transistor of FIG. 4 operate as follows: Whenthe supply voltage U drops below the value of one of the voltages to bestabilized, e.g., when the supply voltage drops below the value of thevoltage U to be stabilized, the collector-emitter voltage of theassociated first pnp transistor T collapses and, therefore, no currentflows in the reference element 2,, but current is still fed to theremaining portion of the series connection of the reference elements viathe additional pnp transistors T T,,, so that only the stabilizedvoltage U is no longer present. The above-mentioned collapse of thecollector-emitter voltage of the second pnp transistor T corresponds toa mode of operation in which this transistor is saturated and in whichthe saturation current would flow off laterally via the insulatingregion to the substrate of the integrated circuit because of theblocking action of the buried layer unless the frame-shaped portion C,.of the collector region C took over the saturation current of therespective transistor. Here, the invention starts from he recognitionthat, through the above embodiment, the saturation current is againsupplied at least to the reference element of the lowest voltage to bestabilized, which is accomplished by the collector(s) of thetransistor(s) driven into saturation then acting as emitter for thatportion of the frame C, which lies opposite to this collector now actingas emitter.

In'case of any further drop in the supply voltage U further voltages tobe stabilized can thus fail one after another, but always only thosewill fail whose value is greater than that of the dropped supplyvoltage, while the other voltages are maintained.

In case of a drop in supply voltage, the failure of the current flowingin the no longer stabilizing reference elements naturally changes thetotal current in the series connection of the reference elements so thatthe Z,, with the exception of the reference element 2,, associated withthe lowest voltage to be stabilized are traversed by different currents,while the current through the reference element 2,, remains constant.Particulafly in the forward-biased diodes, because of theircharacteristics, this results in a change in the stabilized voltagewhich may be disadvantageous depending on the stabilization qualityrequired.

To avoid this disadvantage, the collector regions of the transistors TT,, are advantageously arranged as'shown in FIG. 5. Here, unlike in thearrangement of FIG. 4, only the collector region C of the first pnptransistor, the collector region C of the second pnp transistor, and thecollector region C, of the transistor connected to the lowest voltage Uto be stabilized lie opposite to the emitter region E. The othercollector regions C C,, from the point of view of area, are connected inseries in such a manner that, starting from the collector region C ofthe second transistor, they succeed one another in accordance with therespective index.

The collector region C of the second pnp transistor T and the collectorregion C of the first pnp transistor T are U-shaped and each enclose oneend of the stripshaped emitter region E. The collector region C of thesecond pnp transistor is, in turn, enclosed by the U- shaped collectorregion C of the transistor T connected to the second-highest voltage Uto be stabilized, with the U-shaped arrangement continuing up to thecollector region C, of the transistor T,, connected to the second-lowestvoltage U,,,., to be stabilized.

Compared with the embodiment of FIG. 4, that of FIG. has an additionalcollector region, namely the collector region C so that this lateraltransistor has seven collector regions in accordance with seven voltagesto be stabilized. Accordingly, the collector region C,, corresponds tothe collector region C the collector region C,, to the collector regionC and the collector region C to the collector region C the referencecharacters being added in brackets like in FIG. 4.

By the special arrangement of the individual collector regions as aseries connection from the point of view of area, it is achieved thatthe saturation current which, in the arrangement of FIG. 4, immediatelyflows to the collector C,, in case of saturation is first taken over bythe adjacent collector region because then the collector of thetransistor driven into saturation, in turn, acts as the emitter. Throughthe suitable spatial series arrangement and because of the fact that,when the supply voltage U,, drops, the individual voltages to bestabilized automatically fail one after another and that the associatedpnp transistors, too, are therefore driven into saturation one afteranother, the effect of the respective current takeover from onecollector region on to the other, beginning at the collector region Ccontinues up to the collector region C,,

Thus, however, no current is extracted from the series connection of thereference elements when the individual pnp transistors are driven intosaturation, but the saturation current of the transistor driven intosaturation again flows into the series connection via the collectorregion of the adjacent transistor. Thus, however, no changes in currentoccur within the series connection of the reference elements in case offailure of individual voltages to be stabilized, so that the stilleffective stabilized voltages are not subjected to any change by thefailure of the other voltages.

Based upon the recognition mentioned above, the invention thus takesanother step forward and extends the principle of the utilization of thesaturation current, leaking off into the substrate without this measure,to

each of the pnp transistors except to the one having the frame-shapedportion.

Although in the embodiment of FIG. 5, the individual collector regionsconnected in series from the point of view of area are shown to encloseeach other in the shape of a U, this embodiment is not mandatory.Another arrangement is conceivable in which, respectively, one collectorregion is arranged as a strip behind the other. It must only be insuredthat the subsequent collector regions do not lie opposite to the emitterregion E directly but only via the respective preceding collectorregion.

The other details of the embodiment of FIG. 5 are the same as in FIG. 4,i.e., the embodiment of FIG. 5 also comprises the insulating region I,the base region E, the buried layer BL, and the base contact B.

FIG. 6 shows the arrangement to be derived from FIGS. 4 and 5 for thecircuit of FIG. 3. In this case, it is insured from the outset that thecollector region of the transistor connected to the lowest voltage U tobe stabilized follows from the point of view of area as shown in FIG. 5,the collector region of the transistor associated with the highestvoltage U to be stabilized. Otherwise, FIG. 6 corresponds to FIG. 5.

Particularly advantageous conditions are obtained if, in the embodimentsof FIGS. 4 to 6, those edge por' tions of the respective collectorregions which lie opposite to the emitter region are equally longbecause, in that case, equal currents flow in the individualtransistors. These dimensions have been taken into account in FIG. 6, inwhich the edge lengths are drawn in accordance with this teaching, itbeing considered that, in the comer areas shown as broken lines, noinjection to the respective collector region occurs, of course.

Although FIGS. 4 to 6 show the emitter region as a rectangular, narrowstrip, this embodiment is by no means mandatory. The emitter region may,of course, also have the shape of a more or less curved strip or of asharply bent line. The shape of the emitter region can thus be chosenaccording to the respective application and adapted to the integratedcircuit area available for the lateral transistor.

It is to be understood that the foregoing description of specificexamples of this invention is made by way of example only and is not tobe considered as a limitation on its scope.

What is claimed is:

l. A monolithic integrated voltage stabilizing circuit comprising:

a source of supply voltage;

a plurality of series connected reference elements having tapping pointsfrom which stabilized voltages can be tapped;

a first resistor;

a first npn transistor having a base connected to the tapping point ofthe lowest voltage to be stabilized and having an emitter coupled viasaid first resistor v to ground;

a first pnp diode connected transistor having an emitter coupled to saidsource of supply voltage and having a base and collector coupledtogether and to the collector of said first npn transistor;

a starting resistor coupled between the tapping of the lowest voltage tobe stabilized and said source of supply voltage;

a second pnp transistor having an emitter coupled to said source ofsupply voltage, a base coupled to the base of said first pnp transistorand a collector coupled to the base of said npn transistor via saidplurality of series connected reference elements; and

a plurality of additional pnp transistors (T l T each having emitterscoupled to said source of supply voltage, each having bases coupledtogether and to the base of said second pnp transistor and each of saidplurality having a collector coupled to one of said tapping points ofsaid series connected reference elements.

2. A stabilizing circuit according to claim 1 wherein all pnptransistors (T T are one single lateral transistor having severalcollectors (C C 3. A stabilizing circuit according to claim 2 whereinsaid lateral transistor is designed so that the emitter region (E) isstrip-shaped and located in the center of the base region (B), andwherein the individual collector regions (C C are arranged along thecircumference, over and opposite to, the emitter region, and wherein thecollector region (C,,) connected to the tap of the lowest voltage to bestabilized encloses the other collector regions (C C,,.,).

4. A stabilizing circuit according to claim 2 wherein said lateraltransistor has an emitter region (E) which is strip-shaped and locatedin the center of the base region (B), and wherein the collector regions(C,,, C C,,) of said first pnp transistor (T of said second pnptransistor (1",), and of the last of said plurality of additional pnptransistors (T,,) associated with the tap of the lowest voltage to bestabilized are arranged along the circumference, and opposite to, theemitter region, and wherein the collector region connected to the secondhighest voltage to be stabilized lies opposite to the collector regionof said second pnp transistor (T without lying opposite to the emitterregion, and wherein the collector region of the third from last of saidplurality of additional pnp transistors (C,, is connected to the thirdhighest voltage to be stabilized and lies opposite the collector region(C connected to the second highest voltage to be stabilized withoutlying opposite the emitter region, and wherein the collector region(C,,) connected to the lowest voltage to be stabilized additionallyencloses the other collector regions in the form of a closed frame.

5. A stabilizing circuit according to claim 3 wherein the edge portionsof all collector regions (C C which-lie opposite the emitter region (E)are of the same length.

UNETED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,820,007 Dated June 25, 1974 Inventor(s) 8'W. Hoehn It is certifiedthat error appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

30 Add --,-Foreign Application Priority Date July 31, 1972 Germany 1? 2237 559.3

Signed arid sealed this 8th day of October 1974.

(SEAL) Attest:

McCOY M. GIBSON JR. C. MARSHALL DANN Attesting Officer Commissioner ofPatents USCOMM-DC 603164 69 FORM PC4050 (10-69) V Q u.s. oovuemazmram'rmc on'rc: an o Hun-an UNITED STATES PATENT OFFICE CERTIFICATE OFCORRECTION Patent no; $820,007 Dated June 25, 1974 Inventor(s) i g-W.Hoehn It is certified that error appeats in the above-identified patentand that said Letters Patent are hereby corrected as shown below:

Add -Foreign Application Priority Date July 31, 1972 Germany 1? 22 37559.3

Signed arid sealed this 8th day of October 1974,

(SEAL) Attest:

McCOY M. GIBSON JR. C. MARSHALL DANN Commissioner of Patents AttestingOfficer 9 U.S. GO VUNNENT VRINTXNG OFFICE: I959 O 5*"1'33l DRM PO-I050(10-59)

1. A monolithic integrated voltage stabilizing circuit comprising: asource of supply voltage; a plurality of series connected referenceelements having tapping points from which stabilized voltages can betapped; a first resistor; a first npn transistor having a base connectedto the tapping point of the lowest voltage to be stabilized and havingan emitter coupled via said first resistor to ground; a first pnp diodeconnected transistor having an emitter coupled to said source of supplyvoltage and having a base and collector coupled together and to thecollector of said first npn transistor; a starting resistor coupledbetween the tapping of the lowest voltage to be stabilized and saidsource of supply voltage; a second pnp transistor having an emittercoupled to said source of supply voltage, a base coupled to the base ofsaid first pnp transistor and a collector coupled to the base of saidnpn transistor via said plurality of series connected referenceelements; and a plurality of additional pnp transistors (T2 . . . Tn)each having emitters coupled to said source of supply voltage, eachhaving bases coupled together and to the base of said second pnptransistor and each of said plurality having a collector coupled to oneof said tapping points of said series connected reference elements.
 2. Astabilizing circuit according to claim 1 wherein all pnp transistors (To. . . Tn) are one single lateral transistor having several collectors(Co . . . Cn).
 3. A stabilizing circuit according to claim 2 whereinsaid lateral transistor is designed so that the emitter region (E) isstrip-shaped and located in the center of the base region (B), andwherein the individual collector regions (Co . . . Cn) are arrangedalong the circumference, over and opposite to, the emitter region, andwherein the collector region (Cn) connected to the tap of the lowestvoltage to be stabilized encloses the other collector regions (Co . . .Cn 1).
 4. A stabilizing circuit according to claim 2 wherein saidlateral transistor has an emitter region (E) which is strip-shaped andlocated in the center of the base region (B), and wherein the collectorregions (Co, C1, Cn) of said first pnp transistor (To), of said secondpnp transistor (T1), and of the last of said plurality of additional pnptransistors (Tn) associated with the tap of the lowest voltage to bestabilized are arranged along the circumference, and opposite to, theemitter region, and wherein the collector region connected to the secondhighest voltage to be stabilized lies opposite to the collector regionof said second pnp transistor (T1) without lying opposite to the emitterregion, and wherein the collector region of the third from last of saidplurality of additional pnp transistors (Cn 2) is connected to the thirdhighest voltage to be stabilized and lies opposite the collector region(C2) connected to the second highest voltage to be stabilized withoutlYing opposite the emitter region, and wherein the collector region (Cn)connected to the lowest voltage to be stabilized additionally enclosesthe other collector regions in the form of a closed frame.
 5. Astabilizing circuit according to claim 3 wherein the edge portions ofall collector regions (Co . . . Cn) which lie opposite the emitterregion (E) are of the same length.